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The Institute of Electrical and Electronics Engineers (IEEE) has selected Professor Mircea Stan of the University of Virginia (UVA) and his former mentor at UMass Amherst, Professor of Electrical and Computer Engineering (ECE) Wayne Burleson, to receive the 2024 A. Richard Newton Technical Impact Award in Electronic Design Automation for their 1995 paper based on Stan’s research. According to the IEEE, the award was established “to honor a person or persons for an outstanding technical contribution within the scope of electronic-design automation, as evidenced by a paper published at least 10 years before the presentation of the award.” The winning paper – published in the March 1, 1995, issue of IEEE Transactions on Very Large Scale Integration Systems – was titled Bus-invert Coding for Low-Power I/O.

Stan and Burleson’s pioneering 1995 paper offered an elegant solution to the troublesome issue of inefficient power dissipation in the input/output (I/O) of an integrated circuit.

In their 1995 paper, Stan and Burleson suggested a visionary proposal: “the bus-invert method of coding the I/O, which lowers the bus activity and thus decreases the I/O peak power dissipation by 50 percent and the I/O average power dissipation by up to 25 percent.” 

Stan and Burleson added that “The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power.”

As Stan and Burleson explained the backstory to their paper, “Technology trends and especially portable applications drive the quest for low-power, very-large-scale-integration (VLSI) design. Solutions that involve algorithmic, structural, or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period).” 

Stan and Burleson went on to say that “For complementary metal-oxide-semiconductor (CMOS) circuits, most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit.” 

According to Stan and Burleson, “While it is generally accepted that (because of the large capacitances involved) much of the power dissipated by an integrated circuit is at the I/O, little has been specifically done for decreasing the I/O power dissipation.” Their 1995 paper tackled that specific problem in what has proven to be a groundbreaking way over the past three decades.

Stan is currently the director of the UVA School of Engineering and Applied Science’s Computer Engineering Program and director of the Computer Engineering Virginia Microelectronics Consortium. He received his diploma degree from the Politehnica University of Bucharest in Romania in 1984 and later earned his M.S. and Ph.D. degrees from UMass Amherst in 1994 and 1996, respectively. He teaches in the UVA Department of Electronics and Communication Engineering and does research in high-performance, low-power VLSI, temperature-aware circuits and architecture, embedded systems, and nanoelectronics.

Stan is a member of the Association for Computing Machinery, Eta Kappa Nu, Phi Kappa Phi, and Sigma Xi. He was a recipient of the National Science Foundation CAREER Award in 1997. He was also an associate editor of the IEEE Transactions on Circuits and Systems—Part I: Regular Papers from 2004 to 2008 and the IEEE Transactions on Very Large-scale Integration Systems from 2001 to 2003. Currently, he is an associate editor of the IEEE Transactions on Nanotechnology. He was a Distinguished Lecturer of the IEEE Circuits and Systems Society from 2004 to 2005 and from 2012 to 2013.

Burleson has been in the ECE department at UMass Amherst since 1990. From 2012-2017, he was a Senior Fellow at AMD Research on a team whose research led to the most powerful and green supercomputers in the world. He has also had previous sabbaticals at EPFL, LIRM Montpellier, and Telecom Paris. 

Burleson has also worked as a custom-chip designer and consultant in the semiconductor industry with VLSI Technology, DEC, Compaq/HP, Intel, Rambus, and AMD, as well as several start-ups. His research is in the general area of security engineering and VLSI, including medical devices, radio-frequency identification, lightweight security, post-CMOS circuits, and computer-aided design for low-power, interconnects, clocking, reliability, thermal effects, process variation, and noise mitigation. 

Burleson has published more than 200 papers in refereed publications in these areas and is a Fellow of the IEEE for contributions to integrated-circuit design and signal processing. He has electrical-engineering degrees from the Massachusetts Institute of Technology and the University of Colorado. (June 2024)

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