Architecting for Artificial Intelligence with Emerging Nanotechnology

Sourabh Kulkarni — Sun, 31 Jan 2021 15:39:03 +0000

2021

Abstract:

Artificial Intelligence is becoming ubiquitous in products and services that we use daily. Although the domain of AI has seen substantial improvements over recent years, its effectiveness is limited by the capabilities of current computing technology. Recently, there have been several architectural innovations for AI using emerging nanotechnology. These architectures implement mathematical computations of AI with circuits that utilize physical behavior of nanodevices purpose-built for such computations. This approach leads to a much greater efficiency vs. software algorithms running on von-Neumann processors or CMOS architectures which emulate the operations with transistor circuits. In this paper, we provide a comprehensive survey of these architectural directions and categorize them based on their contributions. Furthermore, we discuss the potential offered by these directions with real world examples. We also discuss major challenges and opportunities in this field.

Authors Sourabh Kulkarni and Sachin Bhat contributed equally to this work.

PDF (In Press)

Publication Type:

Conference

Vol. No.:

Issue No.:

Article No.:

citation:

ACM Journal on Emerging Technologies in Computing Systems (JETC)

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Santosh Khasanvis — Sun, 30 Aug 2015 15:25:45 +0000

2014

Abstract:

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology,
Skybridge^TM, which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.

Nanoscale Computing Fabrics Lab - Noise Mitigation

Architecting for Artificial Intelligence with Emerging Nanotechnology

Abstract:

Publication Type:

Vol. No.:

Issue No.:

pages:

Article No.:

citation:

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Abstract:

Publication Type:

Vol. No.:

Issue No.:

pages:

Article No.:

citation:

Nanoscale Computing Fabrics Lab - Noise Mitigation

Architecting for Artificial Intelligence with Emerging Nanotechnology

Abstract:

Publication Type:

Vol. No.:

Issue No.:

pages:

Article No.:

citation:

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Abstract:

Related Projects:

Publication Type:

Vol. No.:

Issue No.:

pages:

Article No.:

citation: