Nanoscale Computing Fabrics Lab - Nanocircuits

Architecting for Causal Intelligence at Nanoscale

Santosh Khasanvis — Sun, 30 Aug 2015 14:49:16 +0000

Santosh Khasanvis

Mingyu Li

Mostafizur Rahman

Ayan K. Biswas

Mohammad Salehi Fashami

Jayasimha Atulasimha

Supriyo Bandyopadhyay

Csaba Andras Moritz

2015

Abstract:

Machine-learning frameworks such as Bayesian networks are widely acknowledged for their capability to reason under uncertainty. However their massive computational requirement, when implemented on conventional computers, hinders their usefulness in critical problem areas. We propose a non von Neumann machine paradigm purposefully architected with physical equivalence across all layers for solving these problems efficiently. It uses emerging magneto-electric nanoscale devices in a novel mixed-signal circuit framework operating directly on probabilities, without segregation between memory and computation. Based on bottom-up simulations, we show four orders of magnitude performance improvement vs. best-of-breed microprocessors with 100 cores, for Bayesian inference involving a million variables. Smaller problem sizes in the order of a 100 variables can be realized at 12mW power consumption and very low area of about a tenth of a mm². Our vision is to enable solving complex Bayesian problems in real time, while incorporating intelligence capabilities at smaller scales everywhere.

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IEEE Computer, Special Issue on Rebooting Computing

SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs

Sourabh Kulkarni — Sat, 17 Jul 2021 16:31:26 +0000

2021

2021 ISVLSI Nagarajan Ranganathan Best Paper Award

Abstract:

For sub-5nm technology nodes, gate-all-around (GAA) FETs are positioned to replace FinFETs to enable the continued miniaturization of ICs in the future. In this paper, we introduce SkyBridge-3D-CMOS 2.0, a 3D-IC technology featuring integration of stacked vertical GAAFETs and 3D interconnects. It aims to provide an integrated solution to critical technology aspects, especially when scaling to sub-5nm nodes. We address important aspects such as 3D fabric components, CAD tool flow, compact model for the GAAFETs and a scalable manufacturing process. The fabric features junctionless accumulation-mode field effect transistors (JAMFETs) including various configurations with multiple threshold voltages and multiple nanowires per transistor, to meet performance and stand-by power constraints of modern SoCs. Furthermore, we develop BSIM-CMG-based compact models for these device configurations to enable technology assessment using SPICE simulations. To enable scalable manufacturing, we create virtual process decks incorporating etch and deposition models using Process Explorer, an industry standard process emulation tool. Technology assessment using ring oscillators shows that SkyBridge-3D-CMOS 2.0 at the chosen design point, using 16nm gate length and 10-nm nanowires, achieves ∼18% performance and 31% energy efficiency improvement versus 7nm FinFET CMOS. Area analysis of standard cells shows up to 6x benefit versus aggressively scaled 2D-5T cells.

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IEEE Computer Society Annual Symposium on VLSI

Architecting for Artificial Intelligence with Emerging Nanotechnology

Sourabh Kulkarni — Sun, 31 Jan 2021 15:39:03 +0000

Sourabh Kulkarni

Sachin Bhat

Csaba Andras Moritz

2021

Abstract:

Artificial Intelligence is becoming ubiquitous in products and services that we use daily. Although the domain of AI has seen substantial improvements over recent years, its effectiveness is limited by the capabilities of current computing technology. Recently, there have been several architectural innovations for AI using emerging nanotechnology. These architectures implement mathematical computations of AI with circuits that utilize physical behavior of nanodevices purpose-built for such computations. This approach leads to a much greater efficiency vs. software algorithms running on von-Neumann processors or CMOS architectures which emulate the operations with transistor circuits. In this paper, we provide a comprehensive survey of these architectural directions and categorize them based on their contributions. Furthermore, we discuss the potential offered by these directions with real world examples. We also discuss major challenges and opportunities in this field.

Authors Sourabh Kulkarni and Sachin Bhat contributed equally to this work.

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ACM Journal on Emerging Technologies in Computing Systems (JETC)

A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

Sourabh Kulkarni — Mon, 25 Jan 2021 21:04:37 +0000

2021

Abstract:

Three-dimensional integrated circuits (3D-ICs) provide a feasible path for scaling CMOS technology in the foreseeable future. IMEC and IRDS roadmaps project that 3D integration is a key avenue for the IC industry beyond 2024. They project that some form of 3D-IC technology based on nanosheets/nanowires is likely to become mainstream soon. SkyBridge-3D-CMOS (S3DC) is one among the first vertical nanowire-based fine-grained 3D-IC directions which offers paradigm shift in technology scaling as well as design. Rather than die-die and layer-layer stacking, S3DC’s core aspects, from device to circuit style to interconnect, are co-architected in a 3D fabric-centered manner building on a uniform 3D nanowire template. Nanowire-based 3D-IC technologies such as S3DC solve most of the traditional scaling issues of 2D-CMOS but present new manufacturing challenges because of their complex 3D geometry. Therefore, for these directions to become mainstream, a robust wafer-scale manufacturing pathway that addresses these challenges is vital. In this paper, we propose a wafer-scale manufacturing pathway aimed at developing and optimizing the manufacturing process flows of S3DC. Using physics-driven virtual process integration functionalized with design and process parameters, we obtained realistic 3D structures for all the underlying IC elements and finally combined them to build3D standard cells in S3DC. Electrical characterization of resultant structures using process and device simulations were performed while considering the material properties and nanoscale physics effects. Circuit-level simulations accounting for device behavior using SPICE-compatible compact model and circuit interconnect parasitics were carried out to study the impact of variations in process steps such as patterning, lithography, etch, deposition on device and interconnect performance. Our bottom-up simulation results indicate that the proposed pathway is robust enough to be adopted for large-scale production thus paving the way for wide-spread adoption of vertical fine-grained 3D-IC technologies.

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in Proceedings of International Symposium on Quality Electronic Design (ISQED)

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Sourabh Kulkarni — Tue, 15 Oct 2019 13:18:58 +0000

2019

Abstract:

Our European Union’s Horizon-2020 project aims to develop a complete synthesis and performance optimization
methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.
Within the project, we investigate different computing models based on either two-terminal switches, realized with field effect
transistors, resistive and diode devices, or four-terminal switches. Although a four-terminal switch based model offers a significant area advantage, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. In this study, we answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes. As a follow-up work within the project, we will proceed to the fabrication step.

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in Proceedings of Design Automation and Test in Europe (DATE)

Integrated Synthesis Methodology for Crossbar Arrays

Sourabh Kulkarni — Tue, 15 Oct 2019 02:04:06 +0000

2018

Abstract:

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional
technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

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in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance

Sourabh Kulkarni — Tue, 15 Oct 2019 01:58:15 +0000

2019

Abstract:

Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS. They offer area and power efficiency in courtesy of their easyto-fabricate and dense physical
structures consisting of regularly placed crosspoints as computing elements. Depending on the used technology, a crosspoint behaves as a diode, a memristor, a field effect transistor, or a four-terminal switching device. In this study, we comparatively elaborate on these technologies in terms of their capabilities for computing in terms of area, delay, and power consumption. Also, we consider fault tolerance capabilities of the arrays. Due to the stochastic nature of nano-fabrication, nanoarrays have much higher fault rates compared conventional technologies such as CMOS. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and defect or fault rates of the given nanoarray as well as their effects on performance metrics including power, delay, and area.

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IEEE Transactions on Nanotechnology

SkyNet: Memristor-based 3D IC for Artificial Neural Networks

Sourabh Kulkarni — Tue, 26 Sep 2017 15:18:27 +0000

2017

Abstract:

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs. This paper introduces a new fine-grained 3D integrated ASIC technology for ANNs that is the first IC technology for this purpose. Synaptic weights implemented with devices are incorporated in a uniform vertical nanowire template co-locating the memory and computation requirements of ANNs within each neuron. Novel 3D routing features are used for interconnections in all three dimensions between the devices enabling high connectivity without the need for special pins or metal vias. To demonstrate the proof of concept of this fabric, classification of binary images using a perceptron-based feed forward neural network is shown. Bottom-up evaluations for the proposed fabric considering 3D implementations of fabric components reveal up to 21x density, 1.8x power benefits and a 2.6x improvement in delay when compared to 16nm hybrid memristor/CMOS technology.

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in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

Fine-Grained 3D Reconfigurable Computing Fabric with RRAM

Mingyu Li — Wed, 20 Sep 2017 13:56:20 +0000

2017

Abstract:

Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer nonvolatile 3D FPGA, the connectivity between the monolithically stacked RRAMs and underlying CMOS circuits is likely to be limited and lead to large parasitic RCs. In this paper, we propose a fine-grained 3D reconfigurable computing fabric concept. It implements CMOS / RRAM hybrid circuits within the pre-doped vertical nanowire template. Transistors and resistive switches can be integrated with a fine granularity, which reduces the routing overhead between RRAM and CMOS circuits and increases the density. We estimate the density benefit of the proposed fabric to be 27X relative to the monolithic 3D FPGA with stacked RRAMs. Estimated Elmore delays are improved by 5.4X and 2.2X for configuration and normal operation, respectively.

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in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

JiaJun Shi — Tue, 19 Sep 2017 20:08:20 +0000

2016

Abstract:

Monolithic 3D IC (M3D) shows degradation in performance compared to 2D IC due to the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used in M3D to mitigate this degradation. Silicon validated 14nm FinFET data and models are used in a device-to-system evaluation to compare the TR-L partitioned M3D’s (TR-L M3D) performance against the conventional gate-level (G-L) partitioned M3D’s performance as well as standard 2D IC. Extensive cell-level and system-level evaluation, including various device and interconnect process options, shows that the TR-L M3D provides up to 20% improved performance while still maintaining around 30% power saving compared to standard 2D IC. Additionally, the TR-L partitioning design enables M3D with a simplified process flow that leads to 23% lower cost compared to that of G-L partitioning scheme.

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2.5.1 - 2.5.4

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IEEE International Electron Devices Meeting (IEDM)

Nanoscale Computing Fabrics Lab - Nanocircuits

Architecting for Causal Intelligence at Nanoscale

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SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs

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Architecting for Artificial Intelligence with Emerging Nanotechnology

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A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

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Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

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Integrated Synthesis Methodology for Crossbar Arrays

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Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance

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SkyNet: Memristor-based 3D IC for Artificial Neural Networks

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Fine-Grained 3D Reconfigurable Computing Fabric with RRAM

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A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

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