Nanoscale Computing Fabrics Lab - in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Manufacturing Pathway and Experimental Demonstration for Nanoscale Fine-Grained 3-D Integrated Circuit Fabric

Santosh Khasanvis — Sat, 29 Aug 2015 18:30:46 +0000

Mostafizur Rahman

JiaJun Shi

Mingyu Li

Santosh Khasanvis

Csaba Andras Moritz

2015

Abstract:

At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3-D has been long sought as a possible pathway to continue scaling; however, CMOS’s intrinsic requirements are not compatible for fine-grained 3-D integration. In [1], we proposed a truly fine-grained 3-D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS. In Skybridge, device, circuit, connectivity, thermal management and manufacturing issues are addressed in an integrated 3-D compatible manner. At the core of Skybridge’s assembly are uniform vertical nanowires, which are functionalized with architected features for fabric integration. All active components are created primarily using sequential material deposition steps on these nanowires. Lithography and doping are performed prior to any functionalization and their precision requirements are significantly reduced. This paper introduces Skybridge’s manufacturing pathway that is developed based on extensive process, device simulations and experimental metrology, and uses established processes. Experimental demonstrations of key process steps are also shown.

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in press

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Towards Defect-Tolerant Nanoscale Architectures

Santosh Khasanvis — Tue, 18 Mar 2014 15:47:51 +0000

Csaba Andras Moritz

Teng Wang

2006

Abstract:

Nanoscale computing systems show great potential but at the same time introduce new challenges not encountered in the world of conventional CMOS designs and manufacturing. For example, these systems need to work around layout and doping constraints resulting from unconventional bottom-up selfassembly, and need to cope with high manufacturing defect rates and transient faults. Unfortunately, most conventional defecttolerance techniques are not directly applicable in nanoscale systems because they have been designed for very small defect rates. In this paper, we explore built-in defect-tolerance techniques on 2-D semiconductor nanowire (NW) arrays to make designs self-healing. Our approach combines circuit and systemlevel techniques and it does not require defect map extraction, reconfigurable devices, or addressing each cross-point similar to reconfigurable approaches. We show that a defect-tolerant simple processor based on our approach would be still around 3X denser than an 18-nm CMOS version with equivalent functionality; a yield greater than 30% is achieved despite a fabric with 14% defective FETs.

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pp. 331-334

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Image Processing Architecture for Semiconductor Nanowire based Fabrics

Santosh Khasanvis — Tue, 18 Mar 2014 14:58:46 +0000

2008

Abstract:

A new processing architecture for semiconductor nanowire grid fabrics is presented. The system consists of a large number of functionally identical units called cells. Cells are locally interconnected with nearest neighbors, with a limited number of global signals routed from supporting CMOS circuitry. One possible implementation of a digital Cellular Neural Network (CNN) using this architecture is shown. The digital cellular design may be up to 27X denser than an equivalent 18nm CMOS implementation. The system, based on a collective computation model, may also significantly alleviate manufacturing, since 100% fault-free components may not be necessary.

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pp. 677-680

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Manufacturing Pathway and Associated Challenges for Nanoscale Computational Systems

Santosh Khasanvis — Tue, 18 Mar 2014 14:54:41 +0000

2009

Abstract:

We propose one possible manufacturing pathway for realizing nanodevice based computational fabrics that combines self-assembly based techniques with conventional photolithography. This pathway focuses on realizing the fabric as a whole including assembly of nanostructures, functionalization of devices, contacts and interconnects. Furthermore, this pathway is scalable to large systems, as multiple devices are created simultaneously in a self-aligning process step. We discuss the key sequence of steps for achieving nanoscale computational systems using the example of a simple digital logic circuit, and review the associated challenges involved for each of these.

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Nanomanufacturing

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pp. 119-122

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Impact of Process Variation on NASIC Nanoprocessors with 2-way Redundancy

Santosh Khasanvis — Tue, 18 Mar 2014 14:44:21 +0000

2009

Abstract:

Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with builtin fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.

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Variation and Fault Tolerance at Nanoscale

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pp. 737-739

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

3-D Integration Requirements for Hybrid Nanoscale-CMOS Fabrics

Santosh Khasanvis — Sun, 05 Jan 2014 01:22:34 +0000

Pavan Panchapakeshan

Priyamvada Vijayakumar

Pritish Narayanan

Chi On Chui

Csaba Andras Moritz

2011

Abstract:

Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on registration and overlay requirements especially. We address the following questions: (i) How can we mitigate the overlay requirements between nano-manufacturing and conventional lithography steps? (ii) How much overlay precision is necessary
between process steps? and (iii) What is the impact on yield if different overlays are used? We propose and evaluate a new 3D integration approach that combines standard CMOS design rules with nano-manufacturing constraints. For a nanoprocessor design implemented in N3ASIC (a hybrid nanowire-CMOS fabric) we show that a 100% yield is achievable even for overlay precisions achievable with current CMOS manufacturing (3σ=±8nm, ITRS 2009) while still retaining 3X density advantage compared to a projected 16nm CMOS scaled design.

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pp. 849-853

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Integrated Nanosystems with Junctionless Crossed Nanowire Transistors

Santosh Khasanvis — Sun, 05 Jan 2014 01:17:48 +0000

2011

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Junctionless ﬁeld-effect transistors (FETs) are promising emerging devices with simple doping proﬁles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simpliﬁed compared to conventional enhancement-mode FETs. However, junctionless FETs have been discussed exclusively in the context of MOSFET replacement assuming other CMOS manufacturing, circuit and interconnect paradigms to be preserved intact. In this paper we argue for integration of junctionless devices into emerging nanofabrics. We propose junctionless crossed-nanowire FETs (xnwFETs) as the active devices for the Nanoscale Application Speciﬁc Integrated Circuits (NASICs) crossed nanowire fabric. We show that in addition to reducing customization requirements for individual nanodevices, the simpler device doping proﬁle enables a scalable manufacturing pathway for NASICs where alignment and overlay requirements are minimized. In this pathway, a uniform 2-D nanowire grid may be assembled using unconventional or self-assembly based approaches without any overlay constraints. Overlay requirements exist only for subsequent photolithography steps, which is expected to be very precise (3σ = ±3.3nm for 16nm technology node).

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pp. 845-848

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

On-Chip Variation Sensor for Systematic Variation Estimation in Nanoscale Fabrics

Santosh Khasanvis — Wed, 07 Nov 2012 23:31:26 +0000

2012

Abstract:

Parameter variations caused by manufacturing imprecision at the nanoscale are expected to cause large deviations in electrical characteristics of emerging nanodevices and nano-fabrics leading to performance deterioration and yield loss. Parameter variation is typically addressed pre-fabrication, with circuit design targeting worst-case timing scenarios. By contrast, if variation is estimated post-manufacturing, adaptive techniques or reconfiguration could be used to provide more optimal level of tolerance. This paper presents a new on-chip sensor design for nanoscale fabrics that from its own variation, can estimate the extent of systematic variation in neighboring regions. A Monte Carlo simulation framework is used to validate the sensor design. Known variation cases are injected and based on sensor outputs, the extent of systematic variation in physical parameters is calculated. Our results show that the sensor has less than 1.2% error in estimation of physical parameters in 100% of injected variation cases. Based on published experimental data, the sensor estimation is shown to be accurate to within 2 % of the actual physical parameter value for a range of up to 7mm.

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Nanowires

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pp. 1-6

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

N3ASIC Based Nanowire Volatile RAM

admin — Fri, 17 Aug 2012 07:58:38 +0000

Mostafizur Rahman

Pritish Narayanan

Csaba Andras Moritz

2011

Abstract:

As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N3ASIC fabric. Besides, it has the potential to be significantly faster and low leakage alternative to SRAM since high performance nanowire FETs and dynamic logic is used for memory architecture.

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pp. 1097-1101

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Post-CMOS Hybrid Spin-Charge Nanofabrics

admin — Fri, 17 Aug 2012 07:19:03 +0000

Prasad Shabadi

Csaba Andras Moritz

2011

Abstract:

We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much more efficient than in CMOS, these benefits can be lost due to the communication requirements between spin-wave blocks, when implemented with wave guides. This inspired a new type of hybrid nanofabric with spin wave high fan-in functions connected to an interconnect stack similar to CMOS: our analysis shows a delay reduction of up to 10X (8.64ns) along the critical path for a (511;9) parallel counter implemented in this fabric vs. spin-wave only. Similar benefits are also shown for a CLA adder with ~4.2ns delay reduction for 1024 bit CLA adder.

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pp. 1399-1402

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in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Nanoscale Computing Fabrics Lab - in Proceedings of IEEE International Conference on Nanotechnology (IEEE NANO)

Manufacturing Pathway and Experimental Demonstration for Nanoscale Fine-Grained 3-D Integrated Circuit Fabric

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Image Processing Architecture for Semiconductor Nanowire based Fabrics

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Manufacturing Pathway and Associated Challenges for Nanoscale Computational Systems

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Impact of Process Variation on NASIC Nanoprocessors with 2-way Redundancy

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