Nanoscale Computing Fabrics Lab - in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

Integrated Synthesis Methodology for Crossbar Arrays

Sourabh Kulkarni — Tue, 15 Oct 2019 02:04:06 +0000

Ceylan Morgul

Luca Frontini

2018

Abstract:

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional
technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

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SkyNet: Memristor-based 3D IC for Artificial Neural Networks

Sourabh Kulkarni — Tue, 26 Sep 2017 15:18:27 +0000

2017

Abstract:

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs. This paper introduces a new fine-grained 3D integrated ASIC technology for ANNs that is the first IC technology for this purpose. Synaptic weights implemented with devices are incorporated in a uniform vertical nanowire template co-locating the memory and computation requirements of ANNs within each neuron. Novel 3D routing features are used for interconnections in all three dimensions between the devices enabling high connectivity without the need for special pins or metal vias. To demonstrate the proof of concept of this fabric, classification of binary images using a perceptron-based feed forward neural network is shown. Bottom-up evaluations for the proposed fabric considering 3D implementations of fabric components reveal up to 21x density, 1.8x power benefits and a 2.6x improvement in delay when compared to 16nm hybrid memristor/CMOS technology.

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Fine-Grained 3D Reconfigurable Computing Fabric with RRAM

Mingyu Li — Wed, 20 Sep 2017 13:56:20 +0000

2017

Abstract:

Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer nonvolatile 3D FPGA, the connectivity between the monolithically stacked RRAMs and underlying CMOS circuits is likely to be limited and lead to large parasitic RCs. In this paper, we propose a fine-grained 3D reconfigurable computing fabric concept. It implements CMOS / RRAM hybrid circuits within the pre-doped vertical nanowire template. Transistors and resistive switches can be integrated with a fine granularity, which reduces the routing overhead between RRAM and CMOS circuits and increases the density. We estimate the density benefit of the proposed fabric to be 27X relative to the monolithic 3D FPGA with stacked RRAMs. Estimated Elmore delays are improved by 5.4X and 2.2X for configuration and normal operation, respectively.

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Power -Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

JiaJun Shi — Sat, 09 Sep 2017 02:50:20 +0000

JiaJun Shi

Mingyu Li

Csaba Andras Moritz

2017

Abstract:

Design for power-delivery network (PDN) is one of the major challenges in 3D IC technology. In the typical layer-by-layer stacked monolithic 3D (M3D) approaches, PDN has limited accessibility to the device layer away from power/ground source due to limited routability and routing resources in the vertical direction. This results in an incomplete and low-density PDN design and also severe IR-drop issue. Some improved M3D approaches try to enlarge design area to create additional vertical routing resources for robust and high-density PDN design. However, this leads to degradation of design density and in turn diminishes 3D design benefits. Skybridge 3D CMOS (S3DC) is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing critical challenges in 3D IC technology. Skybridge’s core fabric components provide a greater degree of routing capability in both horizontal and vertical directions compared to other 3D approaches which can fully maintain the 3D design density while enabling a robust PDN design. In this paper, we present the PDN design and evaluate the IR drop in S3DC vs. the state-of-the-art transistor-level monolithic 3D IC (TR-L M3D). The typical TR-L M3D approach that can only use low-density PDN shows a severe IR-drop which is out of the standard IR-drop budget. The improved TR-L M3D version that can use high-density PDN meets the requirement of standard IR-drop budget (<5%*VDD) but loses up-to 25% power efficiency and 20% density benefits over 2D compared to the typical TR-L M3D. On the other hand, S3DC maintains its significant benefits over 2D (2.7x power efficiency and 9x density) while using a robust PDN design that has negligible IR-drop (<2%*VDD).

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Towards Automatic Thermal Network Extraction in 3D ICs

Mingyu Li — Thu, 08 Sep 2016 19:17:04 +0000

2016

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Thermal management is one of the critical challenges in 3D integrated circuits. Incorporating thermal optimizations during the circuit design stages requires a convenient automatic method of doing thermal characterization for feedback purposes. In this paper, we present a methodology, which supports thermal characterization by automatically extracting the steady-state thermal modeling resistance network from a post-placement physical design. The method follows a two-level hierarchical approach. It does fine- grained thermal modeling for standard cells, and then at higher level assembles the thermal modeling network of the input physical design by using the built standard cell thermal models, and adding the information on inter-cell connections as well as implemented thermal management features. The methodology has been implemented in Skybridge-3D-CMOS technology, but can be employed in other fine-grained 3D directions such as monolithic 3D CMOS. Large scale benchmarking has been performed, showing the ability of doing automated fine-grained thermal characterization in the order of seconds per thousands of 3D standard cells. In addition, the methodology is employed to highlight implications of added thermal extraction features.

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Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS

Mingyu Li — Thu, 08 Sep 2016 19:14:21 +0000

2016

Abstract:

Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability. Skybridge is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing associated 3D connectivity and manufacturability challenges. Skybridge's core fabric components enable a new 3D IC design approach with vertically-composed logic gates, and provide a greater degree of routing flexibility compared to conventional 2D and 3D ICs leading to much larger benefits and future scalability. In this paper, we present a methodology using relevant metrics to evaluate and quantify the benefits of Skybridge vs. state-of-the-art transistor-level monolithic 3D IC (T-MI) and 2D in terms of routability and its impact on large-scale circuits. This is enabled by a new device-to-system design flow with commercial CAD tools that we developed for large-scale Skybridge IC designs in 16nm node. Evaluation for standard benchmark circuits shows that Skybridge yields up to 1.6x lower routing demand against T-MI with no routing congestion (routing demand to resource ratio < 1) at all metal layers. This 3D routability in conjunction with compact vertical gate design in Skybridge translate into benefits of up to 3x lower power and 11x higher density over 2D CMOS, while TLM-3DIC approach only has up to 22% power saving and 2x density improvement over 2D CMOS.

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in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

Architecting NP-Dynamic Skybridge

Santosh Khasanvis — Sat, 29 Aug 2015 18:34:48 +0000

2015

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This paper introduces a new fine-grained 3D IC fabric technology called NP-Dynamic Skybridge. Skybridge is a family of 3D IC technologies that provides fine-grained vertical integration. In comparison to the original 3D Skybridge, the NP-Dynamic approach enables a more comprehensive logic style for improved efficiency. It addresses device, circuit, connectivity and manufacturability requirements with an integrated 3D mindset. The NP-Dynamic 3D circuit style enables wide range of logic expressions, simple clocking scheme, and reduces buffer requirements. Architected interconnect framework in 3D provides a high degree of connectivity. Bottom-up evaluations for 16-nm NP-Dynamic Skybridge, considering material properties, nanoscale transport, 3D circuit style, 3D placement and layout reveal up to 50x density and 25x power benefits for 4-bit CLA in comparison to 16-nm CMOS at comparable performance. For 4-bit multiplier, NP-Dynamic Skybridge shows up to 90x density benefit and 8x lower power vs. CMOS.

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pp. 169-174

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Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits

Santosh Khasanvis — Sat, 01 Aug 2015 16:34:46 +0000

2015

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Conventional CMOS technology is reaching fundamental scaling limits, and interconnection bottleneck is dominating IC power and performance. Migrating to 3-D integrated circuits, though promising, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Skybridge, a fine-grained 3-D IC fabric technology was recently proposed towards this aim, which offers a paradigm shift in technology scaling and design. In this paper we present specifically architected core Skybridge structures to enable fine-grained connectivity in 3-D intrinsically. We develop predictive models for interconnect length distribution for Skybridge, and use them to quantify the benefits in terms of expected reduction in interconnect lengths and repeater counts when compared to 2-D CMOS in 16nm node. Our estimation indicates up to 10x reduction in longest global interconnect length vs. 16nm 2-D CMOS, and up to 2 orders of magnitude reduction in the number of repeaters for a design consisting of 10 million logic gates. These results show great promise in alleviating interconnect bottleneck due to a higher degree of connectivity in 3-D, leading to shorter global interconnects and reduced power and area overhead due to repeater insertion.

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pp. 175-180

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Architecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features

Santosh Khasanvis — Sat, 01 Aug 2015 16:28:30 +0000

2015

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Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D integration using die to die and layer to layer stacking do not represent true progression , and suffer from their own challenges with lack of intrinsic thermal management being among the major ones. Our proposal for 3-D IC, Skybridge, is a truly fine-grained vertical nanowire based fabric that solves technology scaling challenges, and at the same time achieves orders of magnitude benefits over 2-D CMOS. Key to Skybridge’s 3-D integration is the fabric centric mindset, where device, circuit, connectivity, thermal management and manufacturing issues are co-addressed in a 3-D compatible manner. In this paper we present architected fine-grained 3-D thermal management features that are intrinsic components of the fabric and part of circuit design; a key difference with respect to die-die and layer-layer stacking approaches where thermal management considerations are coarse-grained at system level. Our bottom-up evaluation methodology, with simulations at both device and circuit level, shows that in the best case Skybridge’s thermal extraction features are very effective in thermal management, reducing temperature of a heated region by up to 92%.

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pp. 157-162

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Physically Equivalent Magneto-Electric Nanoarchitecture for Probabilistic Reasoning

Santosh Khasanvis — Sat, 01 Aug 2015 16:12:13 +0000

Santosh Khasanvis

Mingyu Li

Mostafizur Rahman

Mohammad Salehi Fashami

Ayan K. Biswas

Jayasimha Atulasimha

Supriyo Bandyopadhyay

Csaba Andras Moritz

2015

Abstract:

Probabilistic machine intelligence paradigms such as Bayesian Networks (BNs) are widely used in critical real-world applications. However they cannot be employed efficiently for large problems on conventional computing systems due to inefficiencies resulting from layers of abstraction and separation of logic and memory. We present an unconventional nanoscale magneto-electric machine paradigm, architected with the principle of physical equivalence to efficiently implement causal inference in BNs. It leverages emerging straintronic magneto-tunneling junctions in a novel mixed-signal circuit framework for direct computations on probabilities, while blurring the boundary between memory and computation. Initial evaluations, based on extensive bottom-up simulations, indicate up to four orders of magnitude inference runtime speedup vs. best-case performance of 100-core microprocessors, for BNs with a million random variables. These could be the target applications for emerging magneto-electric devices to enable capabilities for leapfrogging beyond present day computing.

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Nanoscale Computing Fabrics Lab - in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

Integrated Synthesis Methodology for Crossbar Arrays

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SkyNet: Memristor-based 3D IC for Artificial Neural Networks

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Fine-Grained 3D Reconfigurable Computing Fabric with RRAM

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Power -Delivery Network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

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Towards Automatic Thermal Network Extraction in 3D ICs

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Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS

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Architecting NP-Dynamic Skybridge

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Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits

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Architecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features

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Physically Equivalent Magneto-Electric Nanoarchitecture for Probabilistic Reasoning