This inter-disciplinary project proposes an unconventional non-volatile magneto-electric computational machine paradigm for causal intelligence problems requiring reasoning or decision-making in the presence of uncertainty (such as in Bayesian Networks) that are computationally infeasible today. Our preliminary evaluation shows up to 5 orders of magnitude performance improvement for Bayesian Networks with over a million random variables vs. state-of-the-art 100 core microprocessors, with an equivalent die-size, which is truly game changing.
This research focuses on transformative new ways to integrate novel devices and structures in vertical nanowires to achieve functional circuits beyond CMOS, while maintaining manufacturability. Fabric features are architected to solve circuit, connectivity and thermal management issues in an integrated manner.
Our research on experimental prototyping involves validation of experimental process steps necessary for large scale assembly of nanowire fabrics, material and device characterizations, and proof of concept demonstration of fabric prototype.
In this project, we propose an approach called Spin Wave Functions (SPWFs) where computation is through wave superposition for practical and compact implementation of ultra-low power, high fan-in complex computational units. Electron spin is the state variable and communication among processing elements is accomplished via collective excitation of spins (also called as spin wave).
We propose a multistate memory capable of storing more than 1 bit in a given cell to overcome the slowdown in area-scaling of CMOS SRAM at nanoscale, enabled by novel graphene nanoribbon crossbars (xGNRs) which exhibit Negative Differential Resistance (NDR). This is used to build a memory cell in conjunction with MOS transistors for access, control and routing.
We explore nanowire-based computing fabrics (NASICs, N3ASICs and NWRAM) for integrated circuit logic and memory. These fabrics are based on an integrated approach spanning multiple design levels including devices, circuits, architecture and manufacturing. Manufacturing challenges, e.g., overlay and registration, are mitigated through careful design choices at multiple levels of abstraction.