Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration

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in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)


pp. 37-42

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We present an integrated approach that combines 3D modeling of nanodevice electrostatics and operations with extensive circuit level validation and evaluation. We simulate crossed nanowire field-effect transistor (xnwFET) structures, extract electrical characteristics, and create behavioral models for circuit level validations. Our experiments show that functional cascaded dynamic circuits can be achieved by optimal selection of device level parameters such as VTH. Furthermore, VTH tuning is achieved through substrate biasing and source and drain junction underlap, which does not pose difficult manufacturability and customization challenges. Circuit level simulationsof up to forty cascaded stages show correct propagation of data and adequate noise margins.