Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology

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IEEE Transactions on Nanotechnology, Special Issue on Revolutionary 3-D Integration

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Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being composed in 2D. In contrast, vertically-composed 3D CMOS has eluded us likely due to the seemingly insurmountable requirement of highly customized complex routing and regional 3D doping to form and connect CMOS pull-up and pull-down networks in 3D. In the current layer-by-layer directions, routing can be worse than 2D CMOS because of the limited pin access. In this paper, we propose Skybridge-3D-CMOS (S3DC), an IC fabric that shows for the first time a pathway to achieve fine-grained static CMOS circuit implementations using the vertical direction while also solving 3D routability. It employs a new fabric assembly scheme based on pre-doped vertical nanowire bundles. It implements circuits in and across nanowires. It utilizes unique connectivity features to achieve CMOS connectivity in 3D with excellent routability. As compared to the usually severely congested monolithic 3D implementations, S3DC eliminates the routing congestions in all benchmarks studied. Further results, for the implemented benchmarks, show 56%-77% reductions in power consumption, 4X-90X increases in density, and 20% loss to 9% benefit in best operating frequencies compared with the transistor-level monolithic 3D technology.