SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs

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Publication Medium:

IEEE Computer Society Annual Symposium on VLSI

Year of Publication:



2021 ISVLSI Nagarajan Ranganathan Best Paper Award


For sub-5nm technology nodes, gate-all-around (GAA) FETs are positioned to replace FinFETs to enable the continued miniaturization of ICs in the future. In this paper, we introduce SkyBridge-3D-CMOS 2.0, a 3D-IC technology featuring integration of stacked vertical GAAFETs and 3D interconnects. It aims to provide an integrated solution to critical technology aspects, especially when scaling to sub-5nm nodes. We address important aspects such as 3D fabric components, CAD tool flow, compact model for the GAAFETs and a scalable manufacturing process. The fabric features junctionless accumulation-mode field effect transistors (JAMFETs) including various configurations with multiple threshold voltages and multiple nanowires per transistor, to meet performance and stand-by power constraints of modern SoCs. Furthermore, we develop BSIM-CMG-based compact models for these device configurations to enable technology assessment using SPICE simulations. To enable scalable manufacturing, we create virtual process decks incorporating etch and deposition models using Process Explorer, an industry standard process emulation tool. Technology assessment using ring oscillators shows that SkyBridge-3D-CMOS 2.0 at the chosen design point, using 16nm gate length and 10-nm nanowires, achieves ∼18% performance and 31% energy efficiency improvement versus 7nm FinFET CMOS. Area analysis of standard cells shows up to 6x benefit versus aggressively scaled 2D-5T cells.