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With recent promising progress on nanoscale devices including semiconductor nanowires and nanowire crossbars, researchers are trying to explore the possibility of building nanoscale computing systems. We have designed a nanoscale application-specific architecture called NASIC, which is based on semiconductor nanowire grids and FETs at crosspoints. In this paper, we propose a built-in redundancy technique to tolerate the defects in our nanoscale architecture. Compared to other fault tolerance techniques, our solution has significant advantages including self-healing, higher density. We evaluate the efficiency of self-healing technique and provide the density comparison with deep sub-micron CMOS technology.