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Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability. Skybridge is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing associated 3D connectivity and manufacturability challenges. Skybridge's core fabric components enable a new 3D IC design approach with vertically-composed logic gates, and provide a greater degree of routing flexibility compared to conventional 2D and 3D ICs leading to much larger benefits and future scalability. In this paper, we present a methodology using relevant metrics to evaluate and quantify the benefits of Skybridge vs. state-of-the-art transistor-level monolithic 3D IC (T-MI) and 2D in terms of routability and its impact on large-scale circuits. This is enabled by a new device-to-system design flow with commercial CAD tools that we developed for large-scale Skybridge IC designs in 16nm node. Evaluation for standard benchmark circuits shows that Skybridge yields up to 1.6x lower routing demand against T-MI with no routing congestion (routing demand to resource ratio < 1) at all metal layers. This 3D routability in conjunction with compact vertical gate design in Skybridge translate into benefits of up to 3x lower power and 11x higher density over 2D CMOS, while TLM-3DIC approach only has up to 22% power saving and 2x density improvement over 2D CMOS.