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Design for power-delivery network (PDN) is one of the major challenges in 3D IC technology. In the typical layer-by-layer stacked monolithic 3D (M3D) approaches, PDN has limited accessibility to the device layer away from power/ground source due to limited routability and routing resources in the vertical direction. This results in an incomplete and low-density PDN design and also severe IR-drop issue. Some improved M3D approaches try to enlarge design area to create additional vertical routing resources for robust and high-density PDN design. However, this leads to degradation of design density and in turn diminishes 3D design benefits. Skybridge 3D CMOS (S3DC) is a recently proposed fine-grained 3D IC fabric relying on vertical nanowires that presents a paradigm shift for scaling, while addressing critical challenges in 3D IC technology. Skybridge’s core fabric components provide a greater degree of routing capability in both horizontal and vertical directions compared to other 3D approaches which can fully maintain the 3D design density while enabling a robust PDN design. In this paper, we present the PDN design and evaluate the IR drop in S3DC vs. the state-of-the-art transistor-level monolithic 3D IC (TR-L M3D). The typical TR-L M3D approach that can only use low-density PDN shows a severe IR-drop which is out of the standard IR-drop budget. The improved TR-L M3D version that can use high-density PDN meets the requirement of standard IR-drop budget (<5%*VDD) but loses up-to 25% power efficiency and 20% density benefits over 2D compared to the typical TR-L M3D. On the other hand, S3DC maintains its significant benefits over 2D (2.7x power efficiency and 9x density) while using a robust PDN design that has negligible IR-drop (<2%*VDD).