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Process variations arise due to processing and masking limitations, and result in random or spatially varying deviation from the designed parameter values. Changes in these parameters cause electrical parameters to vary, such as effective channel length and threshold voltage. These mismatches modify the strength of individual devices resulting in various failures. In this paper, we present a failure analysis of CAM cells under process variation in 32-nm CMOS technology. We investigate the effects of variations in Leff and Vt on the performance and power consumption of CAM cells. Finally, we discuss techniques at circuit and architecture levels to mitigate the effect of process variation on CAM access.