Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration

Publication Files

Publication Medium:

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

pages

pp. 24-31

Year of Publication:

2010

Abstract

Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated framework enables to study in detail the impact of physical parameter variation across all fabric layers for the first time. The framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 40% deviation from nominal. Monte Carlo simulations using the architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. However, given high defect rates in nano-manufacturing, built-in fault tolerance needs to be incorporated for achieving acceptable yields. These techniques are shown to also ameliorate the effects of parameter variation.