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Maintaining power scaling trend and cell stability are critical challenges facing CMOS SRAM at sub-20nm technologies. These challenges primarily stem from the fundamental limitations of MOSFETs, and the rigid device doping and sizing requirements of underlying SRAM design. In this paper, we propose a new volatile memory architecture called Tunnel FET based Random Access Memory (TNRAM) that solves CMOS SRAM scaling challenges through integration of ultra-low power Tunnel FETs (TFETs) in a novel circuit style. It is designed to operate with single type uniform transistors to eliminate nanoscale device sizing requirements, and is customized to prevent SRAM like stability concerns. Analytical projections show significant power benefits; 6T-TRAM has 4.38x lower active power and 174x lower leakage power over HP 6T-SRAM at 16nm technology node.