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Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic
circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. The paper proposes a methodology for analyzing the sources of defects in a nano-manufacturing flow and estimating the resulting systematic yield loss. This methodology allows analyzing the impact of the fabrication process on the systematic yield. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities (or rates). While the focus of the paper is on estimating the mask overlay-limited yield for the NASIC nano-fabric, the proposed approach can be easily adapted to suit other structured nano-fabrics.