On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs

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IEEE Computer Society Annual Symposium on VLSI


pp. 449 - 454

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Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as well as benefits and challenges of a silicon validated 14nm Finfet process design kit (PDK) based TR-L M3D IC technology is explored. TR-L M3D standard cell layout is achieved based on 14nm Finfet design rules and feature sizes. A semi-customized RC extraction methodology is performed for accurate 3D cell RC extraction. After extensive simulation, TR-L M3D cell power, delay and area are evaluated and compared with equivalent 2D cells in the same technology node. System-level benchmarking with several circuits show up to 55% reduced footprint, 25% shorter wire length, and 18% lower power with TR-L M3D vs. 2D CMOS.

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