Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures

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in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch)

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Recent research progress on nanoscale devices such as based on nanowire (NW) crossbars shows great promise towards building nanoscale computing systems. This paper is part of our ongoing effort to develop and evaluate highdensity, defect-tolerant architectures on such fabrics. Our designs are based on Nanoscale Application Specific ICs (NASICs), and are primarily targeted towards microprocessor datapaths. In this paper we propose a new dynamic circuit scheme that enables efficient pipelining and temporary data storage with a 2£ higher throughput than in previously published designs. In addition, we explore builtin defect-tolerance techniques in conjunction with systemlevel CMOS voting and evaluate their effectiveness to mask both defective transistors and broken NWs, as well as combination defects. Furthermore, we introduce a simple defect model for clustered defects. We evaluate the effectiveness of our defect-tolerant designs for both uniformly distributed as well as clustered defects.