Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance

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IEEE Transactions on Nanotechnology



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Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS. They offer area and power efficiency in courtesy of their easyto-fabricate and dense physical
structures consisting of regularly placed crosspoints as computing elements. Depending on the used technology, a crosspoint behaves as a diode, a memristor, a field effect transistor, or a four-terminal switching device. In this study, we comparatively elaborate on these technologies in terms of their capabilities for computing in terms of area, delay, and power consumption. Also, we consider fault tolerance capabilities of the arrays. Due to the stochastic nature of nano-fabrication, nanoarrays have much higher fault rates compared conventional technologies such as CMOS. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and defect or fault rates of the given nanoarray as well as their effects on performance metrics including power, delay, and area.