Biased Voting for Improved Yield in Nanoscale Fabrics

Publication Files

Publication Medium:

in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)


pp. 79-85

Year of Publication:



Best Paper Award


Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that use majority voters to vote on the ‘0’ or 1’ outputs of redundant modules. Novel nanoscale computational fabrics employ new circuit and logic styles where the likelihood of occurrence of faulty ‘1’s and faulty ‘0’s may not be identical. This provides an opportunity for using biased voting (towards logic ‘1’ or ‘0’) to achieve improved yield. In this paper, we investigate
the effectiveness of using biased voters as opposed to majority voters in such nanoscale fabrics. We analyze the Nanoscale Application Specific Integrated Circuits (NASIC) fabric and show that faulty ‘1’s may be up to 12x more likely than faulty ‘0’s, paving the way for applying biased voting successfully. For NASIC modules with a fan-in of 10, biased voting configurations are shown to achieve more than 27% increase in the probability of producing a correct output.