A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC

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IEEE International Electron Devices Meeting (IEDM)


2.5.1 - 2.5.4

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Monolithic 3D IC (M3D) shows degradation in performance compared to 2D IC due to the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used in M3D to mitigate this degradation. Silicon validated 14nm FinFET data and models are used in a device-to-system evaluation to compare the TR-L partitioned M3D’s (TR-L M3D) performance against the conventional gate-level (G-L) partitioned M3D’s performance as well as standard 2D IC. Extensive cell-level and system-level evaluation, including various device and interconnect process options, shows that the TR-L M3D provides up to 20% improved performance while still maintaining around 30% power saving compared to standard 2D IC. Additionally, the TR-L partitioning design enables M3D with a simplified process flow that leads to 23% lower cost compared to that of G-L partitioning scheme.