Variation and Fault Tolerance at Nanoscale

Impact of Process Variation on NASIC Nanoprocessors with 2-way Redundancy

Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with builtin fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.

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Heterogeneous 2-level Logic and its Density and Fault Tolerance Implications in Nanoscale Fabrics

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g.,AND–OR, NOR–NOR, NAND–NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it.

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Parameter Variation Sensing and Estimation in Nanoscale Fabrics

Parameter variations introduced by manufacturing imprecision are becoming more influential on circuit performance. This is especially the case in emerging nanoscale computing fabrics due to unconventional manufacturing steps and aggressive scaling. On-chip variation sensors are gaining in importance since post-fabrication compensation techniques can be employed. In estimation with on-chip variation sensors, however, random variations are masked because of well-known averaging effects during measurements.

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Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation

Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers.

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Biased Voting for Improved Yield in Nanoscale Fabrics

Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that use majority voters to vote on the ‘0’ or 1’ outputs of redundant modules. Novel nanoscale computational fabrics employ new circuit and logic styles where the likelihood of occurrence of faulty ‘1’s and faulty ‘0’s may not be identical. This provides an opportunity for using biased voting (towards logic ‘1’ or ‘0’) to achieve improved yield.

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Nanoscale Application Specific Integrated Circuits

This chapter provides an overview of the Nanoscale Application Specific IC (NASIC) fabric. The NASIC fabric has spun several research directions by multiple groups. This overview is a snapshot of the thinking, techniques and some of the results as of to date. NASICs is targeted as a CMOS-replacement technology. The project encompasses aspects from the physical layer and manufacturing techniques, to devices, circuits and architectures, and is funded by NSF, and FENA/FCRP and CHM/NSEC nanotechnology centers.

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FastTrack: Towards Nanoscale Fault Masking with High Performance

High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuits and logic styles. Development of analytical fault models for nanosystems is necessary to explore the design of novel fault tolerance schemes that could be more effective than conventional schemes.

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