Gene Expression Networks (GENs) attempt to model how genetic information stored in the DNA (Genotype) results in the synthesis of proteins, and consequently, the physical traits of an organism (Phenotype). Deciphering GENs plays an important role in a wide range of applications from genetic studies of the origins of life to personalized healthcare. Probabilistic graphical models such as Bayesian Networks (BNs) are used to perform learning and inference of GENs from genetic data.
Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization.
We show results from ongoing work studying the interaction of process variation and built-in fault resilience intended to handle defects. We find that built-in fault resilience decreases the negative effects of process variation on a streaming nanoprocessor design.
With recent promising progress on nanoscale devices including semiconductor nanowires and nanowire crossbars, researchers are trying to explore the possibility of building nanoscale computing systems. We have designed a nanoscale application-specific architecture called NASIC, which is based on semiconductor nanowire grids and FETs at crosspoints. In this paper, we propose a built-in redundancy technique to tolerate the defects in our nanoscale architecture. Compared to other fault tolerance techniques, our solution has significant advantages including self-healing, higher density.
Nanoscale computing systems show great potential but at the same time introduce new challenges not encountered in the world of conventional CMOS designs and manufacturing. For example, these systems need to work around layout and doping constraints resulting from unconventional bottom-up selfassembly, and need to cope with high manufacturing defect rates and transient faults. Unfortunately, most conventional defecttolerance techniques are not directly applicable in nanoscale systems because they have been designed for very small defect rates.
Recent research progress on nanoscale devices such as based on nanowire (NW) crossbars shows great promise towards building nanoscale computing systems. This paper is part of our ongoing effort to develop and evaluate highdensity, defect-tolerant architectures on such fabrics. Our designs are based on Nanoscale Application Specific ICs (NASICs), and are primarily targeted towards microprocessor datapaths. In this paper we propose a new dynamic circuit scheme that enables efficient pipelining and temporary data storage with a 2£ higher throughput than in previously published designs.
Nanoscale processor designs pose new challenges not encountered in the world of conventional CMOS designs and manufacturing. Nanoscale devices based on crossed semiconductor nanowires (NWs) have promising characteristics in addition to providing great density advantage over conventional CMOS devices. This density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated.
Most proposed architectures for nanoscale computing systems are based on a certain type of 2-level logic family, e.g., AND-OR, NOR-NOR, etc. In this paper, we propose a new fabric architecture that combines different logic families in the same nanofabric. To achieve this we apply very minor modifications on the way a nanogrid is controlled but without changing the basic manufacturing assumptions. This new hybrid 2-level logic based fabric yields higher density for the applications mapped to it. When fault tolerance techniques are added it significantly improves fault tolerance.
Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with builtin fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.