Spin Wave Nanofabric Update

We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing.

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Design Of Spin Wave Functions-Based Logic Circuits

Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transistors. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic.

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Spin Wave Functions Nanofabric Update

We provide a comprehensive progress update on the magnonic spin wave functions nanofabric. Spin wave propagation does not involve any physical movement of charge particles. Information is encoded in the phase of the wave and computation is based on the principle of superposition. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. The coupling mechanism between the spin and charge domain is enabled by the Magneto-Electric (ME) cells.

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Post-CMOS Hybrid Spin-Charge Nanofabrics

We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much more efficient than in CMOS, these benefits can be lost due to the communication requirements between spin-wave blocks, when implemented with wave guides.

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