Cognition and higher order reasoning in the human brain have been shown to adhere closely to probabilistic inference frameworks such as Bayesian networks that support reasoning under uncertainty. We architect a physically equivalent Bayesian network fabric with nanotechnology, employing inherently stochastic spintronic devices in unique recursive analog circuit structures that support Bayesian inference through physical fabric properties. This fabric approach results in many orders of magnitude efficiency improvements over conventional approaches and enables new cognitive applications with millions of random variables that are not possible today.
Artificial Intelligence is becoming ubiquitous in products and services that we use daily. Although the domain of AI has seen substantial improvements over recent years, its effectiveness is limited by the capabilities of current computing technology. Recently, there have been several architectural innovations for AI using emerging nanotechnology. These architectures implement mathematical computations of AI with circuits that utilize physical behavior of nanodevices purpose-built for such computations. This approach leads to a much greater efficiency vs.
Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer nonvolatile 3D FPGA, the connectivity between the monolithically stacked RRAMs and underlying CMOS circuits is likely to be limited and lead to large parasitic RCs.
Gene Expression Networks (GENs) attempt to model how genetic information stored in the DNA (Genotype) results in the synthesis of proteins, and consequently, the physical traits of an organism (Phenotype). Deciphering GENs plays an important role in a wide range of applications from genetic studies of the origins of life to personalized healthcare. Probabilistic graphical models such as Bayesian Networks (BNs) are used to perform learning and inference of GENs from genetic data.
Probabilistic graphical models like Bayesian Networks (BNs) are powerful cognitive-computing formalisms, with many similarities to human cognition. These models have a multitude of real-world applications. New emerging-technology based circuit paradigms leveraging physical equivalence e.g., operating directly on probabilities vs. introducing layers of abstraction, have shown promise in raising the performance and overall efficiency of BNs, enabling networks with millions of random variables.
Probabilistic machine intelligence paradigms such as Bayesian Networks (BNs) are widely used in critical real-world applications. However they cannot be employed efficiently for large problems on conventional computing systems due to inefficiencies resulting from layers of abstraction and separation of logic and memory. We present an unconventional nanoscale magneto-electric machine paradigm, architected with the principle of physical equivalence to efficiently implement causal inference in BNs.
This paper presents the first fully programmable digital cellular design for nanodevice-based computational fabrics. The system has a fully regular structure and consists of a large number of simple functional units called cells. It is programmable, based on a small number of global signals routed from supporting CMOS and associated nanoscale circuitry. The architecture may be adapted to suit a multitude of information-processing paradigms. One example is shown on a two-dimensional (2D) semiconductor nanowire fabric including corresponding circuit-level aspects.
A nanowire-based field-programmable computing platform is presented featuring intrinsic fine-grained device-level reconfiguration without emulation (i.e. no look-up tables involved) using programmable cross-nanowire transistors, and regular physical implementation with relaxed manufacturing requirements at nanoscale. This approach can potentially provide orders of magnitude benefits in terms of area, power and performance vs. scaled CMOS FPGA at lower cost.