Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling.
Graphene is an emerging nanomaterial believed to be a potential candidate for post-Si nanoelectronics, due to its exotic properties. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper, a multi-state memory design is presented that can store multiple bits in a single cell enabled by this xGNR device, called Graphene Nanoribbon Tunneling Random Access Memory (GNTRAM). An approach to increase the number of bits per cell is explored alternative to physical scaling to overcome CMOS SRAM limitations.
Maintaining power scaling trend and cell stability are critical challenges facing CMOS SRAM at sub-20nm technologies. These challenges primarily stem from the fundamental limitations of MOSFETs, and the rigid device doping and sizing requirements of underlying SRAM design. In this paper, we propose a new volatile memory architecture called Tunnel FET based Random Access Memory (TNRAM) that solves CMOS SRAM scaling challenges through integration of ultra-low power Tunnel FETs (TFETs) in a novel circuit style.
Leveraging nanotechnology for computing opens up exciting new avenues for breakthroughs. For example, graphene is an emerging nanoscale material and is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR).
SRAM based memory blocks constitute a major part of state-of-art processor architectures. Increasing complexity and variation in nanometer CMOS fabrication has prompted exploration of memory circuits based on emerging nanofabrics. In this work, we propose a new 8T-Nanowire based RAM (8T-NWRAM) circuit for high density memory arrays. The design is based on N3ASIC, a nanofabric using combination of crosspoint nanowire FETs and integration with metal interconnects. The layout implementation is optimized to reduce bitline load and achieve high performance.
Graphene is an emerging nano-material that has garnered immense research interest due to its exotic electrical properties. It is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper, we present an approach to realize multistate memories, enabled by these graphene crossbar devices.
Graphene exhibits extraordinary electrical properties and is therefore often envisioned to be the candidate material for post-silicon era as Silicon technology approaches fundamental scaling limits. Various Graphene based electronic devices and interconnects have been proposed in the past. In this paper, we explore the possibility of a hybrid fabric between CMOS and Graphene by implementing a novel Graphene Nanoribbon crossbar (xGNR) based volatile Tunneling RAM (GNT RAM) and integrating it with the 3D CMOS stack and layout.
As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N3ASIC fabric.