Architecting for Artificial Intelligence with Emerging Nanotechnology

Artificial Intelligence is becoming ubiquitous in products and services that we use daily. Although the domain of AI has seen substantial improvements over recent years, its effectiveness is limited by the capabilities of current computing technology. Recently, there have been several architectural innovations for AI using emerging nanotechnology. These architectures implement mathematical computations of AI with circuits that utilize physical behavior of nanodevices purpose-built for such computations. This approach leads to a much greater efficiency vs.

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A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

Three-dimensional integrated circuits (3D-ICs) provide a feasible path for scaling CMOS technology in the foreseeable future. IMEC and IRDS roadmaps project that 3D integration is a key avenue for the IC industry beyond 2024. They project that some form of 3D-IC technology based on nanosheets/nanowires is likely to become mainstream soon.

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SkyNet: Memristor-based 3D IC for Artificial Neural Networks

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling.

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Fine-Grained 3D Reconfigurable Computing Fabric with RRAM

Non-volatile 3D FPGA research to date utilizes layer-by-layer stacking of 2D CMOS / RRAM circuits. On the other hand, vertically-composed 3D FPGA that integrates CMOS and RRAM circuits has eluded us, owing to the difficult requirement of highly customized regional doping and material insertion in 3D to build and route complementary p- and n-type transistors as well as resistive switches. In the layer-by-layer nonvolatile 3D FPGA, the connectivity between the monolithically stacked RRAMs and underlying CMOS circuits is likely to be limited and lead to large parasitic RCs.

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Structure Discovery for Gene Expression Networks with Emerging Stochastic Hardware

Gene Expression Networks (GENs) attempt to model how genetic information stored in the DNA (Genotype) results in the synthesis of proteins, and consequently, the physical traits of an organism (Phenotype). Deciphering GENs plays an important role in a wide range of applications from genetic studies of the origins of life to personalized healthcare. Probabilistic graphical models such as Bayesian Networks (BNs) are used to perform learning and inference of GENs from genetic data.

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NP-Dynamic Skybridge: A Fine-Grained 3D IC Technology with NP-Dynamic Logic

A new 3D IC fabric named NP-Dynamic Skybridge is proposed that provides fine-grained vertical 3D integration for future technology scaling. Relying on a template of vertical nanowires, it expands our prior work to incorporate and utilize both n- and p-type transistors in a novel NP-Dynamic circuit-style compatible with true 3D integration. This enables a wide range of elementary logics leading to more compact circuits, simple clocking schemes for cascading logic stages and low buffer requirement.

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On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs

Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as well as benefits and challenges of a silicon validated 14nm Finfet process design kit (PDK) based TR-L M3D IC technology is explored. TR-L M3D standard cell layout is achieved based on 14nm Finfet design rules and feature sizes.

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Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology

Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being composed in 2D. In contrast, vertically-composed 3D CMOS has eluded us likely due to the seemingly insurmountable requirement of highly customized complex routing and regional 3D doping to form and connect CMOS pull-up and pull-down networks in 3D. In the current layer-by-layer directions, routing can be worse than 2D CMOS because of the limited pin access.

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Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Parallel and monolithic 3D integration directions offer pathways to realize 3D integrated circuits (ICs) but still lead to layer-by-layer implementations, each functional layer being composed in 2D first. This mindset causes challenging connectivity, routing and layer alignment between layers when connected in 3D, with a routing access that can be even worse than 2D CMOS, which fundamentally limits their potential.

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