Magneto-electric Approximate Computational Circuits for Bayesian Inference

Probabilistic graphical models like Bayesian Networks (BNs) are powerful cognitive-computing formalisms, with many similarities to human cognition. These models have a multitude of real-world applications. New emerging-technology based circuit paradigms leveraging physical equivalence e.g., operating directly on probabilities vs. introducing layers of abstraction, have shown promise in raising the performance and overall efficiency of BNs, enabling networks with millions of random variables.

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Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology

Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being composed in 2D. In contrast, vertically-composed 3D CMOS has eluded us likely due to the seemingly insurmountable requirement of highly customized complex routing and regional 3D doping to form and connect CMOS pull-up and pull-down networks in 3D. In the current layer-by-layer directions, routing can be worse than 2D CMOS because of the limited pin access.

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Towards Automatic Thermal Network Extraction in 3D ICs

Thermal management is one of the critical challenges in 3D integrated circuits. Incorporating thermal optimizations during the circuit design stages requires a convenient automatic method of doing thermal characterization for feedback purposes. In this paper, we present a methodology, which supports thermal characterization by automatically extracting the steady-state thermal modeling resistance network from a post-placement physical design. The method follows a two-level hierarchical approach.

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Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS

Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability.

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Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization.

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Architecting NP-Dynamic Skybridge

This paper introduces a new fine-grained 3D IC fabric technology called NP-Dynamic Skybridge. Skybridge is a family of 3D IC technologies that provides fine-grained vertical integration. In comparison to the original 3D Skybridge, the NP-Dynamic approach enables a more comprehensive logic style for improved efficiency. It addresses device, circuit, connectivity and manufacturability requirements with an integrated 3D mindset. The NP-Dynamic 3D circuit style enables wide range of logic expressions, simple clocking scheme, and reduces buffer requirements.

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Wave Interference Functions for Neuromorphic Computing

Neuromorphic computing mimicking the functionalities of mammalian brain holds the promise for cognitive capabilities enabling new intelligent applications. However, research efforts so far mainly focused on using analog and digital CMOS technologies to emulate neural activities, and are yet to achieve expected benefits. They suffer from limited scalability, density overhead, interconnection bottleneck and power consumption related constraints. In this paper, we present a transformative approach for neuromorphic computing with Wave Interference Functions (WIF).

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Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits

Conventional CMOS technology is reaching fundamental scaling limits, and interconnection bottleneck is dominating IC power and performance. Migrating to 3-D integrated circuits, though promising, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Skybridge, a fine-grained 3-D IC fabric technology was recently proposed towards this aim, which offers a paradigm shift in technology scaling and design.

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Architecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features

Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D integration using die to die and layer to layer stacking do not represent true progression , and suffer from their own challenges with lack of intrinsic thermal management being among the major ones. Our proposal for 3-D IC, Skybridge, is a truly fine-grained vertical nanowire based fabric that solves technology scaling challenges, and at the same time achieves orders of magnitude benefits over 2-D CMOS.

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Physically Equivalent Magneto-Electric Nanoarchitecture for Probabilistic Reasoning

Probabilistic machine intelligence paradigms such as Bayesian Networks (BNs) are widely used in critical real-world applications. However they cannot be employed efficiently for large problems on conventional computing systems due to inefficiencies resulting from layers of abstraction and separation of logic and memory. We present an unconventional nanoscale magneto-electric machine paradigm, architected with the principle of physical equivalence to efficiently implement causal inference in BNs.

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