Post-CMOS Hybrid Spin-Charge Nanofabrics

We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much more efficient than in CMOS, these benefits can be lost due to the communication requirements between spin-wave blocks, when implemented with wave guides.

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Integrated Device-Fabric Explorations and Noise Mitigation in Nanoscale Fabrics

An integrated device-fabric methodology for evaluating and validating nanoscale computing fabrics is presented. The methodology integrates physical layer assumptions for materials and device structures with accurate 3-D simulations of device electrostatics and operations and circuit level noise and cascading validations. Electrical characteristics of six different Crossed Nanowire Field Effect Transistors (xnwFETs) are simulated and current and capacitance data obtained.

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