Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration

Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated framework enables to study in detail the impact of physical parameter variation across all fabric layers for the first time.

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Embedded Processors based on Spin Wave Functions (SPWFs)

Spin Wave Functions (SPWFs) realize computation with spin waves, offering several benefits and new features over CMOS. SPWF technology potentially opens up new directions for designing microprocessors with increased capabilities over current implementations. Towards this end, as a preliminary work an 8-bit embedded processor is explored here using SPWFs and evaluated in terms of its power, area and performance using analytical estimates. A CMOS 8-bit processor implemented in an equivalent technology node is synthesized with CAD tools for comparison.

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Nanoscale Application Specific Integrated Circuits

This fabric update summarizes recent advances for the Nanoscale Application Specific Integrated Circuits (NASICs) nanoscale computing fabric. We provide a brief overview of NASICs, and discuss recent work at all fabric levels. We present advances in device design and optimization including omega gated and junctionless nanowire field effect transistors, methodologies for validation of functionality and parameter variation evaluation, new circuit-level sequencing schemes and performance optimization techniques.

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3-D Integration Requirements for Hybrid Nanoscale-CMOS Fabrics

Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on registration and overlay requirements especially. We address the following questions: (i) How can we mitigate the overlay requirements between nano-manufacturing and conventional lithography steps?

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Integrated Nanosystems with Junctionless Crossed Nanowire Transistors

Junctionless field-effect transistors (FETs) are promising emerging devices with simple doping profiles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simplified compared to conventional enhancement-mode FETs. However, junctionless FETs have been discussed exclusively in the context of MOSFET replacement assuming other CMOS manufacturing, circuit and interconnect paradigms to be preserved intact.

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Nanoscale Application Specific Integrated Circuits

This chapter provides an overview of the Nanoscale Application Specific IC (NASIC) fabric. The NASIC fabric has spun several research directions by multiple groups. This overview is a snapshot of the thinking, techniques and some of the results as of to date. NASICs is targeted as a CMOS-replacement technology. The project encompasses aspects from the physical layer and manufacturing techniques, to devices, circuits and architectures, and is funded by NSF, and FENA/FCRP and CHM/NSEC nanotechnology centers.

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Integrated Nanowire Systems for Post-CMOS Computing

CMOS faces new device and technology challenges: MOSFETs require ultra-sharp doping profiles and complex processing; integration of devices into circuits requires arbitrary interconnection with overlay precision beyond known manufacturing solutions (3σ=±3nm, 16nm CMOS, ITRS’11[1]). To overcome these challenges, we propose a new nanoscale computing fabric with integrated design of device, interconnect and circuits to minimize manufacturing requirements while providing ultra-dense, high-performance, and low-power solution surpassing scaled CMOS.

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Spin Wave Nanofabric Update

We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing.

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Design Of Spin Wave Functions-Based Logic Circuits

Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transistors. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic.

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Spin Wave Functions Nanofabric Update

We provide a comprehensive progress update on the magnonic spin wave functions nanofabric. Spin wave propagation does not involve any physical movement of charge particles. Information is encoded in the phase of the wave and computation is based on the principle of superposition. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. The coupling mechanism between the spin and charge domain is enabled by the Magneto-Electric (ME) cells.

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