Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures

Recent research progress on nanoscale devices such as based on nanowire (NW) crossbars shows great promise towards building nanoscale computing systems. This paper is part of our ongoing effort to develop and evaluate highdensity, defect-tolerant architectures on such fabrics. Our designs are based on Nanoscale Application Specific ICs (NASICs), and are primarily targeted towards microprocessor datapaths. In this paper we propose a new dynamic circuit scheme that enables efficient pipelining and temporary data storage with a 2£ higher throughput than in previously published designs.

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Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids

Nanoscale processor designs pose new challenges not encountered in the world of conventional CMOS designs and manufacturing. Nanoscale devices based on crossed semiconductor nanowires (NWs) have promising characteristics in addition to providing great density advantage over conventional CMOS devices. This density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated.

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Combining 2-level Logic Families in Grid-based Nanoscale Fabrics

Most proposed architectures for nanoscale computing systems are based on a certain type of 2-level logic family, e.g., AND-OR, NOR-NOR, etc. In this paper, we propose a new fabric architecture that combines different logic families in the same nanofabric. To achieve this we apply very minor modifications on the way a nanogrid is controlled but without changing the basic manufacturing assumptions. This new hybrid 2-level logic based fabric yields higher density for the applications mapped to it. When fault tolerance techniques are added it significantly improves fault tolerance.

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NASICs: A Nanoscale Fabric for Nanoscale Microprocessors

The rapid progress of manufacturing nanoscale devices is pushing researchers toexplore appropriate nanoscale computing architectures for high density beyond the physical limitations of conventional lithography. However, manufacturing and layout constraints, as well as high defect/fault rates expected in nanoscale fabrics, could make most device density lost whenintegrated into computing systems. Therefore, a nanoscale architecture that can deal with those constraints and tolerate defects/faults at expected rates, while still retaining the density advantage, is highly desirable.

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CMOS Control Enabled Single-Type FET NASIC

A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS providing control signals that coordinate the operation of the logic implemented in the nanoscale. In this paper, the new circuit style is explored, examples from a microprocessor design are shown, manufacturing and density implications discussed.

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Image Processing Architecture for Semiconductor Nanowire based Fabrics

A new processing architecture for semiconductor nanowire grid fabrics is presented. The system consists of a large number of functionally identical units called cells. Cells are locally interconnected with nearest neighbors, with a limited number of global signals routed from supporting CMOS circuitry. One possible implementation of a digital Cellular Neural Network (CNN) using this architecture is shown. The digital cellular design may be up to 27X denser than an equivalent 18nm CMOS implementation.

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Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration

We present an integrated approach that combines 3D modeling of nanodevice electrostatics and operations with extensive circuit level validation and evaluation. We simulate crossed nanowire field-effect transistor (xnwFET) structures, extract electrical characteristics, and create behavioral models for circuit level validations. Our experiments show that functional cascaded dynamic circuits can be achieved by optimal selection of device level parameters such as VTH.

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Heterogeneous 2-level Logic and its Density and Fault Tolerance Implications in Nanoscale Fabrics

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g.,AND–OR, NOR–NOR, NAND–NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it.

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Towards Logic Functions as the Device

This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs.

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Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance

Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric.

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