Towards Automatic Thermal Network Extraction in 3D ICs

Thermal management is one of the critical challenges in 3D integrated circuits. Incorporating thermal optimizations during the circuit design stages requires a convenient automatic method of doing thermal characterization for feedback purposes. In this paper, we present a methodology, which supports thermal characterization by automatically extracting the steady-state thermal modeling resistance network from a post-placement physical design. The method follows a two-level hierarchical approach.

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Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS

Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC technologies using Through Silicon Via or Monolithic Inter-layer Via alleviate some of these challenges, they follow a similar layout and routing mindset as 2D CMOS. This is insufficient to address routing requirements in high-density 3D ICs and even causes severe routing congestion at large-scale designs, limiting their benefits and scalability.

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Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Parallel and monolithic 3D integration directions offer pathways to realize 3D integrated circuits (ICs) but still lead to layer-by-layer implementations, each functional layer being composed in 2D first. This mindset causes challenging connectivity, routing and layer alignment between layers when connected in 3D, with a routing access that can be even worse than 2D CMOS, which fundamentally limits their potential.

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Unconventional Nanocomputing with Physical Wave Interference Functions

In this chapter, we introduce a new fully generic computational paradigm for post-CMOS integrated circuits based on emerging wave-like physical phenomenon (e.g. spin waves), called Wave Interference Functions (WIF). Waves offer new features and opportunities for logic circuits with inherent support for multi-valued data representation, communication and computation. Multi-valued information processing occurs through wave interference, and multi-valued communication between processing elements is through wave propagation.

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Architecting Connectivity for Fine-grained 3-D Vertically Integrated Circuits

Conventional CMOS technology is reaching fundamental scaling limits, and interconnection bottleneck is dominating IC power and performance. Migrating to 3-D integrated circuits, though promising, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Skybridge, a fine-grained 3-D IC fabric technology was recently proposed towards this aim, which offers a paradigm shift in technology scaling and design.

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Architecting 3-D Integrated Circuit Fabric with Intrinsic Thermal Management Features

Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D integration using die to die and layer to layer stacking do not represent true progression , and suffer from their own challenges with lack of intrinsic thermal management being among the major ones. Our proposal for 3-D IC, Skybridge, is a truly fine-grained vertical nanowire based fabric that solves technology scaling challenges, and at the same time achieves orders of magnitude benefits over 2-D CMOS.

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Physically Equivalent Magneto-Electric Nanoarchitecture for Probabilistic Reasoning

Probabilistic machine intelligence paradigms such as Bayesian Networks (BNs) are widely used in critical real-world applications. However they cannot be employed efficiently for large problems on conventional computing systems due to inefficiencies resulting from layers of abstraction and separation of logic and memory. We present an unconventional nanoscale magneto-electric machine paradigm, architected with the principle of physical equivalence to efficiently implement causal inference in BNs.

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Wire-Streaming Processors on 2-D Nanowire Fabrics

Most of the research in the field of nanoelectronics has been focused on nanodevices and fabrication aspects and as a result a variety of nanodevice technologies have been demonstrated. By contrast, very little work has been reported on the design and evaluation of circuits and computational architectures using nanodevices. There is similarly not much work on the impact of device and fabric (e.g., the 2-D nanowire array) properties on computing. In this paper, we focus on computing architectures based on silicon nanowires.

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Self-Healing Wire-Streaming Processors on 2-D Semiconductor Nanowire Fabrics

With recent promising progress on nanoscale devices including semiconductor nanowires and nanowire crossbars, researchers are trying to explore the possibility of building nanoscale computing systems. We have designed a nanoscale application-specific architecture called NASIC, which is based on semiconductor nanowire grids and FETs at crosspoints. In this paper, we propose a built-in redundancy technique to tolerate the defects in our nanoscale architecture. Compared to other fault tolerance techniques, our solution has significant advantages including self-healing, higher density.

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Towards Defect-Tolerant Nanoscale Architectures

Nanoscale computing systems show great potential but at the same time introduce new challenges not encountered in the world of conventional CMOS designs and manufacturing. For example, these systems need to work around layout and doping constraints resulting from unconventional bottom-up selfassembly, and need to cope with high manufacturing defect rates and transient faults. Unfortunately, most conventional defecttolerance techniques are not directly applicable in nanoscale systems because they have been designed for very small defect rates.

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