At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3-D has been long sought as a possible pathway to continue scaling; however, CMOS’s intrinsic requirements are not compatible for fine-grained 3-D integration. In , we proposed a truly fine-grained 3-D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS.
Nanoscale computing systems show great potential but at the same time introduce new challenges not encountered in the world of conventional CMOS designs and manufacturing. For example, these systems need to work around layout and doping constraints resulting from unconventional bottom-up selfassembly, and need to cope with high manufacturing defect rates and transient faults. Unfortunately, most conventional defecttolerance techniques are not directly applicable in nanoscale systems because they have been designed for very small defect rates.
A new processing architecture for semiconductor nanowire grid fabrics is presented. The system consists of a large number of functionally identical units called cells. Cells are locally interconnected with nearest neighbors, with a limited number of global signals routed from supporting CMOS circuitry. One possible implementation of a digital Cellular Neural Network (CNN) using this architecture is shown. The digital cellular design may be up to 27X denser than an equivalent 18nm CMOS implementation.
We propose one possible manufacturing pathway for realizing nanodevice based computational fabrics that combines self-assembly based techniques with conventional photolithography. This pathway focuses on realizing the fabric as a whole including assembly of nanostructures, functionalization of devices, contacts and interconnects. Furthermore, this pathway is scalable to large systems, as multiple devices are created simultaneously in a self-aligning process step.
Process variation is expected to persist in the various novel nanoscale fabrics being proposed to replace CMOS. Logic circuits built using non-traditional and bottom-up techniques will need to meet new design rules, such as tolerance of high defect rates and use of regular structures in layout. One circuit fabric type that meets these requirements is grid-based logic, with builtin fault resilience provided by 2-way redundancy. In this work, we show that this fabric design also is able to tolerate substantial process variation in addition to its defect resistance.
Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on registration and overlay requirements especially. We address the following questions: (i) How can we mitigate the overlay requirements between nano-manufacturing and conventional lithography steps?
Junctionless ﬁeld-effect transistors (FETs) are promising emerging devices with simple doping proﬁles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simpliﬁed compared to conventional enhancement-mode FETs. However, junctionless FETs have been discussed exclusively in the context of MOSFET replacement assuming other CMOS manufacturing, circuit and interconnect paradigms to be preserved intact.
Parameter variations caused by manufacturing imprecision at the nanoscale are expected to cause large deviations in electrical characteristics of emerging nanodevices and nano-fabrics leading to performance deterioration and yield loss. Parameter variation is typically addressed pre-fabrication, with circuit design targeting worst-case timing scenarios. By contrast, if variation is estimated post-manufacturing, adaptive techniques or reconfiguration could be used to provide more optimal level of tolerance.
As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N3ASIC fabric.
We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much more efficient than in CMOS, these benefits can be lost due to the communication requirements between spin-wave blocks, when implemented with wave guides.