Parallel and monolithic 3D integration directions realize 3D integrated circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being composed in 2D. In contrast, vertically-composed 3D CMOS has eluded us likely due to the seemingly insurmountable requirement of highly customized complex routing and regional 3D doping to form and connect CMOS pull-up and pull-down networks in 3D. In the current layer-by-layer directions, routing can be worse than 2D CMOS because of the limited pin access.