IEEE Transactions on Nanotechnology

Wave Interference Functions for Neuromorphic Computing

Neuromorphic computing mimicking the functionalities of mammalian brain holds the promise for cognitive capabilities enabling new intelligent applications. However, research efforts so far mainly focused on using analog and digital CMOS technologies to emulate neural activities, and are yet to achieve expected benefits. They suffer from limited scalability, density overhead, interconnection bottleneck and power consumption related constraints. In this paper, we present a transformative approach for neuromorphic computing with Wave Interference Functions (WIF).

PDF icon PDF1.31 MB

Heterogeneous 2-level Logic and its Density and Fault Tolerance Implications in Nanoscale Fabrics

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g.,AND–OR, NOR–NOR, NAND–NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it.

PDF icon PDF960.15 KB

FastTrack: Towards Nanoscale Fault Masking with High Performance

High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuits and logic styles. Development of analytical fault models for nanosystems is necessary to explore the design of novel fault tolerance schemes that could be more effective than conventional schemes.

PDF icon PDF904.07 KB

Integrated Device-Fabric Explorations and Noise Mitigation in Nanoscale Fabrics

An integrated device-fabric methodology for evaluating and validating nanoscale computing fabrics is presented. The methodology integrates physical layer assumptions for materials and device structures with accurate 3-D simulations of device electrostatics and operations and circuit level noise and cascading validations. Electrical characteristics of six different Crossed Nanowire Field Effect Transistors (xnwFETs) are simulated and current and capacitance data obtained.

PDF icon PDF2 MB
Subscribe to RSS - IEEE Transactions on Nanotechnology