IEEE Symposium on Field-Programmable Custom Computing Machines

Parallelizing Applications into Silicon

The next decade of computing will be dominated by embedded systems, information appliances and application specific computers. In order to build these systems, designers will need high-level compilation and CAD tools that generate architectures that eectively meet the needs of each application. In this paper we present a novel compilation system that allows sequential programs, written in C or FORTRAN, to be compiled directly into custom silicon or reconfigurable architectures.

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Exploring Cost-Performance Optimal Designs of Raw Microprocessors

The semiconductor industry roadmap projects that advances in VLSI technology will permit more than one billion transistors on a chip by the year 2010. The MIT Raw microprocessor is a proposed architecture that strives to exploit these chip-level resources by implementing thousands of tiles, each comprising a processing element and a small amount of memory, coupled by a static two-dimensional interconnect. A compiler partitions negrain instruction-level parallelism across the tiles and statically schedules inter-tile communication over the interconnect.

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