Behavioral Synthesis Based on Taylor Expansion Diagrams

Primary Inventors: 

Maciej Ciesielski, Ph.D.

Description: 

Integrated circuits (IC) and systems on chip (SoC) are specified, designed, and modeled using a hardware descriptive language (HDL). Once complete, these HDL models are fed into a high-level synthesis system to produce a fixed data flow graph (DFG). The resulting fixed DFG is utilized by engineers to develop the hardware component. A major limitation of the current synthesis process is its inability to adjust the generated DFG to coincide with particular architectural goal such as design area, delay, latency, power, and computational precision. This novel synthesis method generates a family of DFGs, and transforms them into an architecture optimized for a particular objective.

This innovative technique is based on a canonical, compact, graph-based data structure, called Taylor Expansion Diagram (TED). The technology relies on a TED to transform the behavioral specification of the system into an architecture, optimized for a given objective (performance, area or power). This is accomplished by constructing, ordering, decomposing, and simplifying the TED diagrams.

Applications: 

This exciting technology has the potential to become the foundation for the next generation of high-level synthesis systems. It raises the level of design abstraction from register transfer level (RTL) to algorithmic and behavioral levels. The technique is particularly applicable to verification and behavioral synthesis of dataflow and computation intensive designs. In particular, algorithm-dominant applications, such as 3G wireless, satellite communications, signal processing and video/image processing could benefit greatly from this technology.

Advantages: 

This invention has several key advantages over existing synthesis processes and systems.

  1. It is a systematic approach that does not depend on designer directives.
  2. It drastically reduces the synthesis time and increases the quality of synthesized designs.
  3. It provides an efficient technique for fast architectural space exploration.
  4. It allows the designer to explore an entire family of solutions, rather than a single one.
  5. It does not rely on "side relations" which are predefined as a library of mapping elements.
Licensing Status: 
Available for Licensing and/or Sponsored Research
Patent Status: 

US Patent 7,472,359 issued

Docket: 
UMA 04-20

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For More Information: 

Michael Jaremchuk
Senior Licensing Officer
Commercial Ventures and Intellectual Property
Phone: 413-577-6121
E-Mail: jaremchuk@research.umass.edu