We explore nanowire-based computing fabrics (NASICs, N3ASICs and NWRAM) for integrated circuit logic and memory. These fabrics are based on an integrated approach spanning multiple design levels including devices, circuits, architecture and manufacturing. Manufacturing challenges, e.g., overlay and registration, are mitigated through careful design choices at multiple levels of abstraction. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Tradeoffs between aggressive scaling and yield can be managed with built-in fault tolerance approaches which are part of the fabric itself, and provide adequate resilience against manufacturing defects and parameter variation. Design, simulation and benchmarking of nanowire processor designs vs. equivalent scaled CMOS have been explored. Application drivers include general purpose processors, image processing and programmable computing fabrics. Ongoing work includes experimental prototyping towards realizing nanowire computing fabrics at sub-30 nm dimensions and programmable nanowire fabrics.