We propose a multistate memory capable of storing more than 1 bit in a given cell to overcome the slowdown in area-scaling of CMOS SRAM at nanoscale. This is enabled by novel graphene nanoribbon crossbars (xGNRs) which exhibit Negative Differential Resistance (NDR). These xGNR devices arranged in a grid-structure lead to a memory element with multiple stable states. This is used to build a memory cell in conjunction with MOS transistors for access, control and routing. This multi-bit per cell approach in conjunction with leakage mitigation schemes provides significant benefits in terms of power and density per-bit when compared to CMOS SRAMs at 16nm node, while still having comparable performance. As graphene technology matures, MOS transistors can be replaced with graphene devices for even further benefits.
This project was in collaboration with Prof. Roger Lake's group at University of California, Riverside.